1. Field of the Invention
The present invention relates to a semiconductor memory and, more particularly, to a semiconductor memory suitably used as a memory, such as a DRAM, having sense amplifiers for receiving data of a memory cell corresponding to a selected word line via a bit line and amplifying the received data.
2. Description of the Related Art
Recently, in semiconductor memories represented by DRAMs with increasing capacity, an internal step-down voltage lower than an external power-supply voltage is often used as a bit line voltage determined by the stored electric charge of a memory cell, for the purpose of reducing power consumption.
In a sense amplifier which rewrites a memory cell of a DRAM by amplifying output microcharge from the memory cell, however, the driving capability lowers and the rewrite time increases as the voltage lowers. This increases the cycle time and access time of the DRAM. To shorten this rewrite time, an overdrive type sense amplifier has been proposed as disclosed in Japanese Patent Laid-Open No. 2-18784 or 5-62467.
FIG. 1 is a diagrammatic view showing a partial configuration of a DRAM using the conventional overdrive type sense amplifier. In this DRAM, a large number of memory cell arrays are formed in a matrix manner on a chip, and sense amplifiers are included in one-to-one correspondence with the respective memory cell arrays.
Referring to FIG. 1, a memory cell 1 includes one MOS transistor and one capacitive element. Although only one memory cell 1 is shown in FIG. 1, in practice a large number of memory cells 1 are arrayed in a matrix manner. The gate of the transistor of each memory cell 1 is connected to a word line WL corresponding to this memory cell 1. The drain of this transistor is connected to a bit line BL corresponding to the memory cell 1.
A row decoder 2 decodes a row address signal and activates a word line WL connected to a memory cell 1 to be accessed, from among word lines WL formed in one-to-one correspondence with rows of the memory cell arrays formed in a matrix manner. A column decoder 3 decodes a column address signal and selects a pair of bit lines BL and /BL connected to a memory cell 1 to be accessed, from among pairs of bit lines BL and /BL formed in one-to-one correspondence with columns of the memory cell arrays formed in a matrix manner. The column decoder 3 turns a corresponding column gate 5 on and connects the selected pair of bit lines BL and /BL to a data bus.
Reference numerals 4.sub.-1 to 4.sub.-n denote flip-flop sense amplifiers formed in one-to-one correspondence with the pairs of bit lines BL and /BL. Each sense amplifier amplifies a differential voltage generated on a pair of bit lines BL and /BL in accordance with electric charge stored in the capacitive element of the memory cell 1 accessed in data read. The column gate 5 described above is a column selecting transistor for connecting a pair of bit lines BL and /BL corresponding to an output signal from the column decoder 3 to the data bus. A bit line precharge/equalize circuit 7 precharges the input/output nodes of a pair of bit lines BL and /BL and a flip-flop to a precharge voltage VPR (typically VII/2).
Reference numeral 8 denotes a signal line to which high-potential terminals of flip-flops 6 of the sense amplifiers 4.sub.-1 to 4.sub.-n are connected together. A signal on this signal line 8 is represented by PSA. Reference numeral 9 denotes a signal line to which low-potential terminals of the flip-flops 6 are connected together. A signal on this signal line 9 is represented by NSA. Each flip-flop 6 starts being activated when the signals PSA and NSA change to high and low levels, respectively, and these levels reach certain levels.
Reference numeral 11 denotes a p-type MOS transistor connected between the signal line 8 and the power supply of an external voltage VCC; 12, a p-type MOS transistor connected between the signal line 8 and the power supply of an internal step-down voltage VII; and 13, an n-type MOS transistor connected between the signal line 9 and the power supply of ground voltage. These transistors 11 to 13 constitute a driving circuit (sense amplifier driver) of the sense amplifiers 4.sub.-1 to 4.sub.-n. A sense amplifier driver control circuit 10 controls ON/OFF of the three transistors 11 to 13.
In the above arrangement, to write data in a memory cell 1, the row decoder 2 decodes a row address signal and activates a word line WL connected to the memory cell 1 in which the data is to be stored. Also, the column decoder 3 decodes a column address signal and outputs a column selecting signal to the gate of the corresponding column selecting transistor 5, such that a pair of bit lines BL and /BL connected to the memory cell 1 in which the data is to be stored are connected to the data bus.
One of the bit lines BL and /BL changes to high level and the other changes to low level in accordance with the data to be written, and the corresponding electric charge is stored in the capacitive element of the accessed memory cell 1. When the activation of the word line WL by the row decoder 2 is stopped after that, the transistor of the accessed memory 1 is turned off, and the charge stored in the capacitive element is kept stored. Consequently, the data is stored in the memory cell 1.
To read out data from a memory cell 1, the row decoder 2 decodes a row address signal and activates a word line WL connected to the memory cell 1 from which the data is to be read out. Consequently, a differential voltage corresponding to the charge amount stored in the capacitive element of the memory cell 1 to be accessed is generated on a pair of bit lines BL and /BL.
When the transistors 11 to 13 are turned on at the respective appropriate timings after that, the signals PSA and NSA start changing to high and low levels, respectively. When these signals PSA and NSA reach certain levels, the flip-flop 6 of the sense amplifier starts being activated and operates in a direction in which the differential voltage on the pair of bit lines BL and /BL increases.
The column decoder 3 decodes a column address signal and outputs a column selecting signal to the corresponding column selecting transistor 5, thereby connecting the pair of bit lines BL and BL, connected to the memory cell from which the data is to be read out, to the data bus. Consequently, the data read from the memory cell 1 onto the bit lines BL and /BL is amplified and output via the data bus, or rewritten in the memory cell 1.
In the overdrive type sense amplifier, when the flip-flops 6 of the sense amplifiers 4.sub.-1 to 4.sub.-n are to be driven by turning the transistors 11 to 13 on or off, the p-type MOS transistor 11 and the n-type MOS transistor 13 are first turned on to supply the external voltage VCC higher than the internal step-down voltage VII as a memory stored voltage to the signal line 8.
When the voltage level of a pair of bit lines BL and /BL reaches the memory stored voltage, the p-type MOS transistor 11 is turned off, the p-type MOS transistor 12 is turned on, and a voltage at the memory stored voltage level is supplied to the signal line 8. In this way, the time of rewrite to the memory cell 1 is shortened by driving the pair of bit lines BL and /BL by using the external voltage VCC higher than the internal step-down voltage VII in the initial stages of driving.
Recently, a fast cycle memory such as an FCRAM (Fast Cycle Random Access Memory) described in Japanese Patent Application No. 9-145406 has been proposed, and higher rewrite speed is being increasingly demanded. The conventional method is capable of achieving high speed to some extent by overdriving but inapplicable to a memory that operates at very high cycle time.